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1. #Using modelsim altera how to
2. #Using modelsim altera code
3. #Using modelsim altera simulator

They core_name_bb.v files are green checked in compilation on modelSim while the core_name_INST.v files don't go through so I just excluded these files from the project tab listing on modelSim (not sure if that's the factor).

#Using modelsim altera code

My own code tend to have expected values but the connections to the output of these IP core modules give "z".įinal point: There are files associated with the creation of these IP core through megaWizard. Start simulating by choosing the top level module - loads and I can view the waveforms of some signals.Compile on modelSim, all files get green checks (indicating fine).Add existing files from my own project that is written in Verilog (a bunch of.Create new project under a new arbitrary directory.My procedure in setting up this simulation is as the following: I'm not sure if i'm missing any special steps here simulating the IP blocks. The input signals for these blocks such as clock, clk_en and aclr are set properly. For simple stuff like a log2 function (common before the $clog2 function was added) you can safely `include inside your design unit (module, interface, etc).I'm trying to simulate (functional Test) a project that contains both my own codes and some instances of Altera Floating Point IP Core generated using MegaWizard on ModelSim.Īll the instantiated IP blocks such as ALTFP_DIV, ALTFP_LOG, ALTFP_ADD_SUB are producing no outputs (result being "z"). Typing is a bit odd in SystemVerilog, so if you need to use a package across multiple files, import is the way to go to get consistent typing across modules. I haven't tried this style with packages but I don't see why it wouldn't work. Import TimerPackage::* parameter TimerAction P_TIMER_ACTION Old style ports: You can do something like this: I'm not sure if that that can precede a parameter list, but it can precede a port list. Import in module: SV-2009 allows you to import after the module name.Outside the module ($unit): If you import outside of a module/interface/class, you put the package in some semi-global space called $unit.NOTE: You must compile the package first! Explicit type: You can use TimerPackage::TimerAction as the parameter type.In SystemVerilog you can import packages in a few places. Doing `include will copy the content of the include file into the design unit you're compiling, hence the duplicate definition error. What I've had the most luck with is compiling the package on its own like you would a module rather than include. In this example, the file name is plldesign.vhd. Compiles the top-level VHDL Design File with the ModelSim software. Compiles the VHDL Design File (.vhd) Definition generated by the IP Catalog with the ModelSim software. The auto generated modelsim script compiles it as needed.Īdmittedly, I only write SystemVerilog on and off, and I've had similar issues with packages. Compiles the alteramf.vhd, 220model.vhd, 220pack.vhd libraries.

#Using modelsim altera how to

I could look into how to do that in SystemVerilog, however I'm now just wondering how this is normally done.Įdit: NVM not sure why but trying the packages/pkg_timer.sv method now works. This is similar to what happens in C / C++ if you include a file twice (from within the same file), to get around it you use: #ifndef _FILE_NAME_H This then fails in Quartus with "identifier TimerPackage" is already declared in the previous scope. įinally I tried changing my package file to timer.pkg and using a `include from the top of every file that needs that package definition. This of course fails as when it tries to compile a file that uses my package. However when I go to tools->run simulate tool->RTL simulation, Modelsim opens and tries to run: Test_run_msim_rtl_verilog.do which seems to be an auto generated script that compiles all my (non-testbench) files EXCEPT my package file, and then calls my msim_compile.do script. Vlog -sv -work work +incdir+PATH/packages I have Quartus set up to use a custom compile script for modelsim, which is called msim_compile.do and looks like. I then tried moving the package definition into another file packages/pkg_timer.sv, added that to my list of files at the top and all is great. package TimerPackage Īt first I had this at the top of my Timer.sv file, but then it only works if my files are compiled in the correct order, which with just one package is fine, I can just make sure Timer.sv is first in the list, but that sounds like bad practice. To allow passing this in from other modules I have the enum defined in a package. I want to use an enum here for clarity, so I can have ACTION_NONE and ACTION_TOGGLE. File and Directory Pathnames Several ModelSim commands have arguments that point to files or directories.

#Using modelsim altera simulator

key that ends a line is shown in the command examples.